Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications, including personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones, among others. Program code and system data, such as a basic input/output system (BIOS) which can be used in personal computing systems, are typically stored in flash memory devices.
Flash memories, comprised of a number of strings formed of one or more memory cells, are typically arranged into array architectures, e.g., a matrix. Two common types of flash memory array architectures are the “NAND” and the “NOR” architectures.
In the NOR array architecture, the floating gate memory cells of the memory array are typically arranged in a matrix. The NOR architecture floating gate memory array is accessed using a row decoder to activate a row of floating gate memory cells by selecting a word select line coupled to their gates. The data values of the row of selected memory cells are then placed on the column sense lines, a data value being indicated by the flow of current corresponding to a particular cell being in a programmed state or an erased state.
A NAND architecture also has its array of floating gate memory cells arranged in a matrix such that the control gates of each floating gate memory cell transistor of the array are typically coupled in rows by word select lines. However, each memory cell is not directly coupled to a column sense line. Instead, the memory cells are electrically coupled together in series, source to drain, between a source line and a column sense line, i.e., bit line, with the drain terminal for each transistor in a string being oriented towards the column sense line.
The NAND architecture memory array is also accessed using a row decoder activating a row of memory cells by selecting a word select line, e.g., row select line, coupled to their gates. A high bias voltage is applied to a selected gate's drain line SG(D). The word select lines coupled to the gates of unselected memory cells of each string are driven to operate the unselected memory cells of each group as pass transistors so that they pass current, e.g., at Vpass, in a manner that is unrestricted by their stored data values. In this manner, a selected transistor is tested for its ability to conduct current, which flows through each group of series-coupled transistors, restricted only by the selected memory cells of each string, thereby placing the current encoded data values of the row of selected memory cells on the column sense lines.
Memory cells in a NAND array architecture can be configured, e.g., programmed, to a desired state. That is, electric charge can be placed on, or removed from, the floating gate of a memory cell to put the cell into any of a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., a 1 or 0. Flash memory multi state memory cells, multibit cells, or multilevel cells, which are referred to hereinafter using the term multilevel cells (MLCs), can be programmed into more than two possible states. MLCs allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 1110, 1000, 1010, 0010, 0110, and 0000.
MLC memory stores multiple bits on each cell by using different threshold voltage (Vt) levels for each state that is stored. The difference between adjacent Vt distributions may be very small for a MLC memory device as compared to a SLC memory device. The reduced margins between adjacent Vt distributions, e.g., program states, can increase the difficulty associated with distinguishing between adjacent program states, which can lead to problems such as reduced data read and/or data retrieval reliability.
Memory device fabricators are continuously seeking to increase performance. However, the scaling of memory cells is limited by the need to increase and/or maintain coupling between a control gate and a floating gate while minimizing the interference between adjacent floating gates. One method of increasing performance of a floating gate memory cell involves placing more memory cells in the same or a smaller area on a memory device. Unfortunately, this can lead to increased parasitic coupling of the gate stacks.
As NAND array architectures are scaled to smaller physical dimensions, the effects of charge located proximate any particular memory cell structure increases. Thus, charge stored on a floating gate of one memory cell can have an increasingly greater influence on the operation of adjacent memory cells as the distance between the semiconductor substrate pillars of adjacent memory cells decreases. Capacitive coupling increases between the structures forming the memory cells as transistors are formed closer together in more dense arrays. Quantitatively, capacitance is the ratio of charge and voltage (C=Q/V), with voltage being proportional to the product of electric field strength and distance. Therefore, as distance decreases in the denominator of the ratio, capacitance increases for a particular amount of charge.